1. Field of the Invention
The present invention relates to integrated circuit memory devices, and more particularly, to an integrated circuit memory device having a hierarchical word line structure including main-word and sub-word lines.
2. Description of the Related Art
A hierarchical word line configuration having main-word lines and sub-word lines has been necessarily adopted for dynamic random access memory (DRAM) device having a large capacity of 256 Mb or above. Since the main-word lines and the sub-word lines are separately driven, the power dissipation can be reduced. Also the pitch of the main-word lines does not need to be strict, which is helpful in the manufacture of large scale devices. Such a word structure is disclosed, for example, in U.S. Pat. Nos. 5,416,748; 5,596,542; 5,764,585; and 5,781,498, all of which are hereby incorporated herein by reference as if fully set forth herein.
In DRAM devices, power supply voltages such as positive voltage Vcc and reference ground voltage Vss are required to be constant regardless of variations in the temperature and noise interference. Within a memory device the voltage Vcc is typically generated by an internal supply voltage generator. The supply voltage is referred to as internal Vcc (IVC). IVC has a unique DC level, for example, IVC is 5 V, 3.3 V, 2.8 V, or 2 V.
Some circuit elements in DRAM devices require a boosted voltage V.sub.BST greater than the IVC level. For instance, a word line driver must supply a boosted voltage to gates on storage cell transistors (see U.S. Pat. No. 5,673,225). The boosted voltage must be greater than the IVC by twice the threshold voltage of the cell transistor.
Referring to FIG. 1, a conventional DRAM device with hierarchical word line structure is shown. The DRAM device has a typical `quarter pitch` layout in which 4 sub-word lines and 4 bit lines make the unit pitch of the cell array. A main-word line MWL corresponds to four sub-word lines SWL1-SWL4 which are coupled to an array of memory cells 10. A main-word line (MWL) decoder 20 uses an on-chip boosted power supply voltage V.sub.BST and generates a main-word decode signal MD in response to a portion A3-An of a row address. The main-word decode signal MD swings between the ground voltage Vss and the boosted voltage V.sub.BST. A sub-word line (SVL) predecoder 30 is responsive to the other portion A1 and A2 of the row address and generates four sub-word predecode signals PX1-PX4. When in the stand-by state, all of the sub-word predecode signals PX1-PX4 remain at the Vss level (i.e., logic low level), but during the active stage only one of which stays at the V.sub.BST level (i.e., logic high level).
Four SWL decoders 40-1 through 40-4 correspond to the sub-word predecode signals PX1-PX4 respectively and are supplied with both the IVC and V.sub.BST. Each of the SWL decoder 40-1 through 40-4 generates two sub-word decode signals WDi and WDiB (where i=1, 2, 3, or 4) in response to a corresponding one of the sub-word predecode signals PX1-PX4. During the stand-by state, all of the sub-decode signals WD1, WD2, WD3 and WD4 remain at the Vss level, but in the active state one of the sub-decode signals WD1, WD2, WD3 and WD4 transitions to the V.sub.BST level. All of the sub-decode signals WD1B, WD2B, WD3B and WD4B remain at the IVC level in the stand-by state while in the active state at the Vss level.
Four SWL drivers 50-1 through 50-4 correspond to the sub-word lines 40-1 through 40-4 (or the SWL decoders SWL1-SVL4), respectively. Each SWL driver 50-i consists of three N-channel MOS transistors Mi1, Mi2, and Mi3 (where i=1, 2, 3, or 4). Each SWL driver 50-i generates a sub-word drive signal SDi in response to the main-word decode signal MD and its corresponding sub-word decode signals WDi and WDiB and provides the sub-word drive signal SDi onto its corresponding sub-word line SWLi. As is well known, the sub-word lines are generally boosted above Vcc+V.sub.T (where V.sub.T is the threshold voltage of a MOS transistor) to increase noise margin and overcome the threshold drop of the cell access transistor.
In the active state, the main-word line MWL is driven to the V.sub.BST level by the MWL decoder 20 so that the node Ni within each SWL driver 50-i rises to the V.sub.BST -V.sub.T level (where V.sub.T is the threshold voltage of each transistor therein). Thereafter, when the sub-decode signals WDi and WDiB of a selected SWL decoder 40-i go to the V.sub.BST and Vss levels, respectively, depending upon the row addresses A1 and A2, the node Ni begins to be boosted due to the gate-to-drain capacitance of the pull-up transistor Mi1 so that the transistor Mi2 is shut off and provides isolation between the main-word line MWL and the node Ni. Such a self-boosting effect enables the corresponding sub-word line SWLi to be driven to the fully high voltage level of the sub-decode signal WDi (i.e., the V.sub.BST level). The pull-down transistor Mi3 acts as a current sinker to discharge the corresponding sub-word line SWLi while the main-word line MWL and the sub-decode signal WDiB remain at the Vss and IVC levels, respectively.
Gate oxide is an important element of the MOS transistors. This thin dielectric layer can break down, resulting in gate shorts, during a long or strong application of electric field across the oxide. Oxide breakdown is generally believed to be caused by positive charge buildup.
As discussed above, in the conventional DRAMs with the hierarchical word line arrangement, since the main-word line decoder 20 and the sub-word line drivers 50-1 through 50-4 are supplied with the boosted voltage V.sub.BST or above, there may be a high probability that the MOS transistors therein will have poor gate oxide reliability.
To solve the above problem, a MWL decoder and SWL drivers using the internal power supply voltage IVC has been proposed as shown in FIG. 2. Referring to FIG. 2, the conventional DRAM device has the same arrangement as that shown in FIG. 1 with the exception that the MWL decoder 20a and the SWL drivers 50a-1 through 50a-4 are provided with the internal power supply voltage IVC instead of V.sub.BST as in the embodiment of FIG. 1. In FIG. 2, the same parts as those shown in FIG. 1 are represented with like reference numerals and to avoid description duplication, accordingly, their explanation will be omitted.
The structure of FIG. 2 may help to provide an improved gate oxide reliability, but another problem may be encountered when it is adopted for a memory device which utilizes a low power voltage supply, for example, 2 volts or below. This problem will be explained below.
Referring again to FIG. 2, in the active state, the main-word line MWL is driven to the IVC level by the MWL decoder 20a so the node Ni within each SWL driver 50a-i rises to the IVC-V.sub.T. Thereafter, when the sub-decode signals WDi and WDiB of a selected SWL decoder 40-i go to the V.sub.BST and Vss levels respectively, the node Ni is finally boosted up to a level of IVC-V.sub.T +V.sub.BST =2IVC+V.sub.T as a result of the self-boosting effect.
For example, if it were assumed that the IVC and the V.sub.T are 3 volts and 0.6 volts respectively, the node Ni would be boosted up to the voltage of 6.6 (=2.times.3+0.6) volts so that the pull-up transistor Mil can fully drive the corresponding sub-word line SWLi up to the V.sub.BST level of 4.2 (=3+2.times.0.6) volts.
However, if the IVC is assumed to be 2 volts, then the node Ni will be boosted up to the voltage of 4.6 volts. This voltage may not be enough to drive the corresponding sub-word line SWLi up to the fall V.sub.BST level of 3.2 volts, causing the increased precharge time delay and the reduced noise margin. In addition, the lower the power supply voltage, the more serious such a negative effect. Consequently, the word line driving architecture of FIG. 2 may have a limitation in low voltage operation.